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| PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS FEATURES * Sixteen 1.2V LVCMOS / LVTTL outputs * LVCMOS / LVTTL clock input * Maximum output frequency: 150MHz * Output skew: TBD * Propagation delay: 3.5ns (typical) * 3.3V core/1.2V output operating supply mode * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free RoHS-compliant packages GENERAL DESCRIPTION The ICS8316 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer with 1.2V LVCMOS Outputs HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8316 single ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. IC S Guaranteed output and part-to-part skew characteristics along with the 1.2V output makes the ICS8316 ideal for high performance, single ended applications that also require a limited output voltage. BLOCK DIAGRAM PIN ASSIGNMENT GND GND OED VDDO QD3 QD2 QD1 QD0 CLK VDDO 4 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 4 24 23 22 VDDO QC0 QC1 QC2 QC3 GND OEC GND QA0:QA3 QA0 QA1 QA2 OEA 4 QB0:QB3 QA3 GND ICS8316 21 20 19 18 17 OEB 4 QC0:QC3 OEA CLK OEC QD0:QD3 QB3 QB2 QB1 GND QB0 OED 32-Lead VFQFN 5mm x 5mm x 0.95 package body K Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8316AK http://www.icst.com/products/hiperclocks.html 1 VDDO REV. A DECEMBER 22, 2005 OEB VDD PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS Type Power Output Power Input Input Power Input Output Input Output Output Pullup Pullup Pullup Description Output supply pins. Bank A clock outputs. LVCMOS / LVTTL interface levels. Power supply ground. Bank A output enable pin. Controls enabling and disabling of QA0:QA3 outputs. LVCMOS / LVTTL interface levels. Pulldown Clock input. LVCMOS / LVTTL interface levels. Core supply pin. Bank B output enable pin. Controls enabling and disabling of QB0:QB3 outputs. LVCMOS / LVTTL interface levels. Bank B clock outputs. LVCMOS / LVTTL interface levels. Bank C output enable pin. Controls enabling and disabling of QC0:QC3 outputs. LVCMOS / LVTTL interface levels. Bank C clock outputs. LVCMOS / LVTTL interface levels. TABLE 1. PIN DESCRIPTIONS Number 1, 16, 24, 25 2, 3, 4, 5 6, 11, 17, 19, 30, 32 7 8 9 10 12, 13, 14, 15 18 20, 21, 22, 23 26, 27, 28, 29 Name VDDO QA0, QA1, QA2, QA3 GND OEA CLK VDD OEB QB3, QB2, QB1, QB0 OEC QC3, QC2, QC1, QC0 QD0, QD1, QD2, QD3 Bank D clock outputs. LVCMOS / LVTTL interface levels. Bank D output enable pin. Controls enabling and disabling 31 OED Input Pullup of QD0:QD3 outputs. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance VDDO = 1.2 5% Test Conditions Minimum Typical 4 VDDO = 1.26V TBD 51 51 15 Maximum Units pF pF k k TABLE 3A. OUTPUT ENABLE Control Inputs OE[A:D] 0 1 AND CLOCK ENABLE FUNCTION TABLE Outputs Qx0:Qx3 Hi-Z Active TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs OE[A:D] 1 1 CLK 0 1 Outputs Qx0:Qx3 LOW HIGH 8316AK http://www.icst.com/products/hiperclocks.html 2 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 34.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V, VDDO = 1.2V5%, TA = 0C TO 70C Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 1.14 Typical 3.3 1.2 TBD TBD Maximum 3.465 1.26 Units V V A A TABLE 4B. LVCMOS DC CHARACTERISTICS, TA = 0C TO 70C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK OEA:OED CLK OEA:OED VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDO = 1.2V 5%; NOTE 1 VDDO = 1.2V 5%; NOTE 1 -5 -150 VDD*0.7 VDD*0.3 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A V V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagram. TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.2V5%, TA = 0C TO 70C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) tR/tF odc Output Frequency Propagation Delay Low to High; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Output Rise Time; NOTE 4 Output Duty Cycle 20% to 80% 3.5 TBD TBD 650 50 Test Conditions Minimum Typical Maximum Units 150 MHz ns ps ps ps % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 8316AK http://www.icst.com/products/hiperclocks.html 3 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS PARAMETER MEASUREMENT INFORMATION 2.7V5% 0.6V5% V DD VDDO SCOPE Qx V DDO Qx 2 LVCMOS GND V DDO Qy 2 tsk(o) -0.6V5% 3.3V CORE/1.2V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW Part 1 Qx V DDO 2 Qx0:Qx3 VDDO 2 Part 2 Qy V DDO 2 tsk(pp) Qx0:Qx3 tsk(b) VDDO 2 PART-TO-PART SKEW BANK SKEW (where x denotes outputs in the same bank) QA0:QA3, QB0:QB3, QC0:QC3, QD0:QD3 t PW t CLK VDD 2 V DDO 2 QA0:QA3, QB0:QB3, QC0:QC3, QD0:QD3 VDDO 2 t PD PERIOD odc = t PW t PERIOD x 100% PROPAGATION DELAY OUTPUT DUTY CYCLE/PLUSE WIDTH/PERIOD 80% 20% tR 80% 20% tF Clock Outputs OUTPUT RISE/FALL TIME 8316AK http://www.icst.com/products/hiperclocks.html 4 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN JA vs. 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W TRANSISTOR COUNT The transistor count for ICS8316 is: 416 8316AK http://www.icst.com/products/hiperclocks.html 5 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS FOR PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX 32 LEAD VFQFN TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL N A A1 A3 b ND NE D D2 E E2 e L 0.30 1.25 1.25 5.00 BASIC 2.25 5.00 BASIC 2.25 0.50 BASIC 0.40 0.50 3.25 3.25 0.18 0.80 0 MINIMUM NOMINAL 32 --0.25 Ref. 0.25 0.30 8 8 1.00 0.05 MAXIMUM Reference Document: JEDEC Publication 95, MO-220 8316AK http://www.icst.com/products/hiperclocks.html 6 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8316AK ICS8316AK 32 Lead VFQFN tray 0C to 70C ICS8316AKT ICS8316AK 32 Lead VFQFN 2500 tape & reel 0C to 70C ICS8316AKLF TBD 32 Lead "Lead-Free" VFQFN tray 0C to 70C ICS8316AKLFT TBD 32 Lead "Lead-Free" VFQFN 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8316AK http://www.icst.com/products/hiperclocks.html 7 REV. A DECEMBER 22, 2005 |
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